It is known from “Frequent Value Encoding For Low Power Data Buses” Jun Yang et al, Association for Computing Machinery (ACM) Transactions on Design Automation of Electronic Systems, Volume 9, No. 3, July 2004, Pages 354 to 384 to encode data values to be transmitted so as to reduce switching activity on external buses for the purpose of reducing power consumption. However, this technique has the disadvantage that extra circuit resources and power are consumed by first encoding the data values to be transmitted and then subsequently decoding these values. Also, the encoding and decoding of the data values introduces a time delay.
It is known from “Reordering Memory Bus Transactions For Reduced Power Consumption” Bruce R. Childers et al. ACM SIGPLAN Workshop On Languages, Compilers, and Tools for Embedded Systems, during ACM SIGPLAN Conference On Programming Language Design and Implementation (PLDI'2000, June 2000) to examine with hardware the data words within a cache line being transferred to or from memory so as to determine a new order for the data words to be transferred in order to reduce switching activity and accordingly energy consumption. This additional hardware consumes power which detracts from the energy saved by reducing the switching activity on the buses. The additional hardware is also a disadvantageous complexity and cost overhead, and incurs a latency penalty due to the time taken to calculate a new order of transmission.
Thus, both Yang and Childers reduce the power consumed by the bus, but at the expense of latency. In some situations the latency incurred may be unacceptable. It is desirable to produce a system that improves the performance of data transfers over the bus without adversely affecting the latency of the system.
In the present application, the term “bus” is taken to mean a collection of one or more conductors. A bus can be a one-to-one connection, a one-to-many connection, a many-to-one connection, or a many-to-many connection. A bus may or may not connect devices via interconnect circuitry.